1. Field of the Invention
The present invention relates to an output circuit, a light-receiver circuit using the same, and a photocoupler.
2. Description of Related Art
An output circuit that outputs digital signals using a totem-pole output circuit is formed of two-stage or three-stage transistors. Further, a circuit provided at a former stage of the output circuit, e.g., a comparator, a differential amplifier, is formed of four-stage or five-stage transistors to cope with high-speed operation. Furthermore, a bias circuit that drives these circuits needs to be formed of an equal or larger number of stages of transistors.
In the middle of start-up of a power supply voltage, the output circuit having fewer number of stages of transistors firstly starts up. However, the comparator, the differential amplifier, the bias circuit and so on that are located at the former stages require high rising voltage. The output circuit can be normally controlled only after the former-stage circuits start up. This makes the output from the output circuit unstable. This means that an unstable signal is supplied to a circuit located at the subsequent stage connected to an output terminal of the output circuit. Thus, the unstable output from the output circuit may cause malfunction in the subsequent circuit, and may cause destruction of the subsequent circuit in the worst case. To prevent such problems, it is necessary to stabilize the output voltage from the output circuit until when the power supply voltage sufficiently increases to allow all the circuits to perform normal operations.
In manufacturing such a stable circuit by ICs, the circuit is preferably manufactured by a small number of manufacturing processes for the purpose of reducing the cost. Active elements are preferably composed of only NPN transistors without using PNP transistors.
FIG. 6 shows a configuration of an output circuit 1 according to a related art. However, only NPN transistors are used as active elements used in the output circuit 1 in FIG. 6 for the reason noted above, and the output circuit 1 has a configuration of a totem-pole output circuit.
As shown in FIG. 6, the output circuit 1 includes a bias circuit 10, a differential amplifier 20, a comparator 30, and an output stage circuit 40.
The bias circuit 10 includes NPN transistors Q11 to Q14, resistors R11 to R14, and diodes D11 to D13.
The NPN transistor Q11 has a collector connected to a power supply voltage VCC, an emitter connected to a node N11, and a base connected to a node N12. The diodes D11 to D13 are connected in series between the node N11 and a node N13. The resistor R12 has one end connected to the node N13, and the other end connected to a node N14. The resistor R13 has one end connected to the node N15. N13, and the other end connected to a node N15. The NPN transistor Q12 has a collector connected to the node N14, an emitter connected to a node N16, and a base connected to the node N15. The NPN transistor Q13 has a collector and a base connected to the node N15, and an emitter connected to a ground terminal GND. The resistor R14 has one end connected to the node N16, and the other end connected to the ground terminal GND. The resistor R11 has one end connected to the power supply voltage VCC, and the other end connected to the node N12. The NPN transistor Q14 has a collector connected to the node N12, an emitter connected to the ground terminal GND, and a base connected to the node N14.
The differential amplifier 20 includes NPN transistors Q21 to Q28, resistors R21 to R23, and a diode D21. The resistor R21 has one end connected to the power supply terminal VCC, and the other end connected to a node N21. The resistor R22 has one end connected to the power supply terminal VCC, and the other end connected to a node N22. The NPN transistor Q21 has a collector and a base connected to the node N21, and an emitter connected to the node N22.
The NPN transistor Q22 has a collector connected to the node N21, an emitter connected to a node N23, and a base connected to a node N26. The NPN transistor Q23 has a collector connected to the node N22, an emitter connected to a node N24, and a base connected to the node N26. The NPN transistor Q24 has a collector connected to the node N23, an emitter connected to a node N25, and a base connected to a differential input terminal VIN1. The NPN transistor Q25 has a collector connected to the node N24, an emitter connected to the node N25, and a base connected to a differential input terminal VIN2.
The NPN transistor Q26 has a collector connected to the power supply terminal VCC, an emitter connected to the node N26, and a base connected to the node N12. The diode D21 has an anode connected to the node N26, and a cathode connected to a node N27. The resistor R23 has one end connected to the node N27, and the other end connected to a node N28. The NPN transistor Q27 has a collector and a base connected to the node N28, and an emitter connected to the ground terminal GND. The NPN transistor Q28 has a collector connected to the node N28, an emitter connected to the ground terminal GND, and a base connected to the node N28.
The comparator 30 has one input terminal CIN1 connected to the node N22, and the other input terminal CIN2 connected to the node N21. Further, the comparator 30 outputs an inversion output with respect to the input of the input terminal CIN1 from an output terminal COUT1, and outputs an inversion output with respect to the input of the input terminal CIN2 from an output terminal COUT2.
The output stage circuit 40 includes NPN transistors Q41 to Q45, resistors R41 and R42, and a diode D41. The NPN transistor Q42 has a collector connected to the power supply terminal VCC, an emitter connected to a node N41, and a base connected to the output terminal COUT2 of the comparator 30. The resistor R41 has one end connected to the node N41, and the other end connected to the ground terminal GND. The resistor R42 has one end connected to the power supply terminal VCC, and the other end connected to a node N42.
The NPN transistor Q41 has a collector connected to the node N42, an emitter connected to a node N43, and a base connected to the output terminal COUT1 of the comparator 30. The NPN transistor Q43 has a collector connected to the node N43, an emitter connected to the ground terminal GND, and a base connected to the node N41. The NPN transistor Q44 has a collector connected to the power supply terminal VCC, an emitter connected to a node N44, and a base connected to the node N42. The diode D41 has an anode connected to the node N44, and a cathode connected to the output terminal VOUT. The NPN transistor Q45 has a collector connected to an output terminal VOUT, an emitter connected to the ground terminal GND, and a base connected to the node N43.
Hereinafter, an operation of the output circuit 1 will be described. First, an operation of the bias circuit 10 will be described. The NPN transistors Q12 to Q14 and the resistors R12 to R14 constitute a bandgap circuit. By setting the voltage of the node N13 to a certain voltage (Vref), a base voltage VbQ11 of the NPN transistor Q11 is determined by a base-emitter voltage VbeQ11 of the NPN transistor Q11 and the diodes D11 to D13 that are connected in series in the forward direction. Specifically, the base voltage VbQ11 is the value expressed by the following expression.VbQ11=Vref+(3×Vf)+VbeQ11=Vref+(4×Vf)
The symbol Vf denotes a forward voltage of a diode, and also corresponds to a base-emitter voltage Vbe of the NPN transistor Q11. The base-emitter voltage of any other NPN transistor also corresponds to Vf.
In the differential amplifier 20, the NPN transistors Q22 and Q23 together with the NPN transistors Q24 and Q25 that form a differential pair form a cascode connection, and each base of the NPN transistors Q22 and Q23 is connected to the node N26. Further, the NPN transistor Q21 is connected between the nodes N21 and N22. According to this configuration, the amplitude of the output of the differential amplifier 20, which is the input of the comparator 30 is limited, thereby achieving a high-speed operation in the differential amplifier 20.
Since the NPN transistors Q26 and Q11 have the common base, a base voltage VbQ26 of the NPN transistor Q26 is equal to the base voltage VbQ11 of the NPN transistor Q11. When a base-emitter voltage of the NPN transistor Q26 is denoted by VbeQ26 and the base voltages of the NPN transistors Q22 and Q23 are respectively denoted by VbQ22 and VbQ23, the following expression is satisfied.
      VbQ    ⁢                  ⁢    22    =            VbQ      ⁢                          ⁢      23        =                            VbQ          ⁢                                          ⁢          26                -                  VbeQ          ⁢                                          ⁢          26                    =                                    VbQ            ⁢                                                  ⁢            11                    -                      VbeQ            ⁢                                                  ⁢            11                          =                              Vref            +                          (                              4                ×                Vf                            )                        -            Vf                    =                      Vref            +                          (                              3                ×                Vf                            )                                          
Thus, the voltage of the NPN transistors Q22 and Q23, which is the voltage of the node N26 is fixed to Vref+(3×Vf).
Further, a current IcQ27, which is the current flowing in a current path in which the NPN transistor Q26, the diode D21, the resistor R23, and the NPN transistor Q27 are connected in series, is determined by the following expression.IcQ27=(Vref+Vf)/R23
The NPN transistors Q27 and Q28 constitute a current mirror. Thus, a constant current Io in accordance with the mirror ratio of the NPN transistor Q27 to the NPN transistor Q28 flows as the operational current of the differential pair transistors Q24 and Q25 with respect to the current IcQ27. The symbol attached to the resistor R23 also indicates the resistance value of the resistor. The symbols attached to other resistors also indicate the resistance values of the respective resistors.
The voltages supplied to the input terminals Vin1 and Vin2 are denoted by V1 and V2, respectively. When V1>V2, the NPN transistor Q24 is ON, and the NPN transistor Q25 is OFF. Thus, the voltages of the nodes N22 and N21 that are outputs of the differential amplifier 20, or voltages VCIN1 and VCIN2 of the input terminals CIN1 and CIN2 of the comparator 30 are as follows.VCIN1=VCC−R21×Io VCIN2=VCC 
Thus, VCIN1<VCIN2 is satisfied. As described above, inversion outputs of the input terminals CIN1 and CIN2 are output from the output terminals COUT1 and COUT2 of the comparator 30, respectively. Thus, when output voltages of the output terminals COUT1 and COUT2 are denoted by VCOUT1 and VCOUT2, respectively, VCOUT1>VCOUT2 is satisfied. In summary, the high-level signal is output from the output terminal COUT1 of the comparator 30, and the low-level signal is output from the output terminal COUT2 thereof.
Since the high-level signal is output from the output terminal COUT1, the NPN transistor Q41 is ON in the output stage circuit 40. Further, since the NPN transistor Q41 is ON, the voltage of the node N41 increases and the NPN transistor Q43 is ON. Further, since the NPN transistor Q43 is ON, the voltage of the node N43 decreases and the NPN transistor Q45 (low-side transistor) is OFF.
On the other hand, the low-level signal is output from the output terminal COUT2. Thus, the NPN transistor Q42 is OFF, the voltage of the node N42 reaches the power supply voltage VCC, and the NPN transistor Q44 (high-side transistor) is ON. Accordingly, the NPN transistor Q45 (low-side transistor) is OFF, the NPN transistor Q44 (high-side transistor) is ON, and the voltage of the output terminal VOUT is in the high level.
On the other hand, when V1<V2, the NPN transistor Q24 is OFF, and the NPN transistor Q25 is ON. Accordingly, the voltages VCIN1 and VCIN2 of the input terminals CIN1 and CIN2 of the comparator 30 are as follows.VCIN1=VCC VCIN2=VCC−R22×Io 
Thus, VCIN1>VCIN2 is satisfied. The inversion outputs of the input terminals CIN1 and CIN2 are output from the output terminals COUT1 and COUT2 of the comparator 30, respectively, where VCOUT1<VCOUT2 is satisfied. In short, the low-level signal is output from the output terminal COUT1 of the comparator 30 and the high-level signal is output from the output terminal COUT2 thereof.
Since the low-level signal is output from the output terminal COUT1, the NPN transistor Q41 is OFF, the voltage of the node N41 drops to the ground voltage GND, which turns off the NPN transistor Q43 in the output stage circuit 40. Since the NPN transistor Q43 is OFF, the voltage of the node N43 increases, which turns on the NPN transistor Q45 (low-side transistor).
On the other hand, since the high-level signal is output from the output terminal COUT2, the NPN transistor Q42 is ON, the voltage of the node N42 decreases, and the NPN transistor Q44 (high-side transistor) is OFF. Accordingly, the NPN transistor Q45 (low-side transistor) is ON, the NPN transistor Q44 (high-side transistor) is OFF, and the voltage of the output terminal VOUT is made low.